The Designation And Implementation Of SW/HW Design For Image Processing Platform Based On TS201

The requirements people ask for the image process have become higher and higher for both IPA (Image Processing Algorithm) and IPP (Image Processing Platform) due to the development of the IPT (Image Processing Technology). For the moment, the IPA has already been quite effective, it's difficult to make a further improvement for the algorithm,but the image processing platform can still be ameliorated and renovated for the different applications and requirements. The hardware and software co-design for the IPP is a very good solution which can cater to the applications and requirements of consumer better. The FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) framework can make their respective advantages complementary to each other, which can improve the performance of the IPP greatly. The unique link-ports of the TS201 can provide greater performance for the real-time image transfer and process, especially for those situations which require for high input-output speed.In this paper, the dual-DSP and dual-FPGA image processing platform has been proposed to meet the requirements of the relevant project. The general image processing system is based on the embedded system and the image processing platform is designed under the background of project. The ADSP TS201 of the ADI and the XC6SLX100-3CSG484I of the Xilinx have been chosen to build the dual-DSP and dual-FPGA platform. The ADSP TS201 is treated as the core processor, while the XC6SLX100-3CSG484I is used as the core component of the underlying algorithm module and the interface controller. By using this platform, the whole system has been designed as a configurable framework. The image transmission between the computer and the detector is supported by the Camera Link interface. The feasibility of the scheme has been argued and discussed in detail, the way how to build the 16-bit grayscale images processing module and relevant analysis of the implementation results have also been presented. The grayscale images processing module mainly includes the Image Smooth Module, the Corner Detection Module and the Lossless Compression CODEC Module, in which the SUSAN algorithm is used in the corner detection module, Paradigm Huffman Co/Decoding method is chosen to build the Lossless Compression CODEC Module and some simple algorithm are used in the Image Smooth Module, such as the median filter module, the maximum(minimum) filter module and median filter module.The debugging process of the whole system has also been presented in the paper. The receive method of the link ports, the configuration of the SDRAM and the debugging process of the clock chip have been discussed and presented in the paper in detail. In general, the image processing platform proposed in this paper has realized the hardware and software co-design, and this platform has already been successfully used in an image process system.