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On-Chip Nor Flash Controller Implementation Based On Hardware Wear Leveling Algorithm

Posted on:2018-09-14Degree:MasterType:Thesis
Country:ChinaCandidate:S T XuFull Text:PDF
GTID:2348330518471034Subject:Electronic Science and Technology
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Owing to the advantages of Flash,like large capacity,high speed,low power and non-volatile,Flash is becoming more and more important in peoples' daily lives.Before updating data in Flash,sector erase must be operated first.Since the erase time of each sector has an upper limit,those sectors that were erased more than others would break more quickly,then the use time of Flash will be shortened.If the erase operations are distributed to the whole Flash evenly to make the erase times of all sectors more similar,the Flash can be used for a longer time.This is the Wear Leveling of Flash.In this study,we design an embedded Nor Flash controller based on hardware wear leveling algorithm in order to reduce software's cost.Four modules,which are wear leveling,,address mapping,garbage collection and Flash interface unit,are implemented by Verilog.Every time a write request arrives,the sector that has the minimum erase time will be found by heap-sort,the virtual address will be connected to the sector's physical address,and the address mapping list will be updated.When the number of garbage sectors reaches a threshold value,garbage collection will start.We also constructed a SoC on the basis of this Flash controller to verify its function and performance.Finally,the result shows that the operation time of initialization,heap deletion and read in hardware wear leveling algorithm is at most 14,16.4 and 17.8 times faster than that in software algorithm respectively.At the meantime,the read and write operations to the Flash are not influenced too much.
Keywords/Search Tags:Nor Flash, Wear Leveling, Hardware Implementation, Heap-sort, Verilog
PDF Full Text Request
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