Hardware Implementation Of Critical Algorithm For Hand Detection

In recent years,the object detection algorithm has been deeply studied in the field of computer vision.The wide application of the object detection algorithm,hand detection algorithm and other image processing algorithms has an inseparable relationship with continuous progress of hardware platforms.Object detection algorithm and hand detection algorithm has a large amount of computation.In the process of hardware implementation of hand detection algorithm,how to make circuit design meet both performance requirements and area constraints becomes an important issue for engineers to consider.In order to facilitate hand detection,the hardware implementation of a pretreatment filtering algotithm has also become an important component.First of all,this paper studies the preprocessing of Gauss filter.The Gauss filter can effectively reduce the noise.Peak signal to noise ratio of the image increases from 22.11 to 30.42.Gauss filter makes the texture of the object clearer,which is good for object detection.The traditional hardware implementation of Gauss filter calculates the sum of nine numbers at four levels by utilizing eight full adders.But the critical path of full adder is long and the logic delay almost four times of the full adder's logic delay.In this paper,one kind of optimizing implementation of Gauss filter was studied.The new implementation proposed in this article uses three kinds of new structure,i.e.Carry Save Adder(CSA),4-2 compressor,and tree structure for compressing attends.After optimizing,only one full adder is needed.Compared with the traditional implementation,the proposed method reduces the logic delay about 32.48%.Secondly,this paper introduces the flow of hand detection algorithm.Hand detection includes three parts:building pyramid of the image,histogram of oriented gradient(HOG)features extraction,and matching of deformable part models.Through the analysis of the characteristics of the hand detection algotithm,it is concluded that computing eciprocal square roots in the HOG features extraction stage is a key operation.Reciprocal square roots(RSR)is studied.RSR algorithm for float-point must use float-point units which have larger area than fixed-point units.So the research on RSR algorithm for fixed-point(FxRSR)is necessary.A design of high-throughput 16-bit fixed-point complex reciprocal/square-root unit(Design A)has been studied.This approach uses an interpolation algorithm based on the 2-D cubic convolution and must use very large lookup tables.So this paper proposes a new 16-bit fixed-point RSR algorithm based on piecewise linear fitting and only one cycle of Newton iteration.This proposed method obtains the initial value of Newton iteration by using eight segment linear fitting.One cycle of Newton interation can improve the accuracy of computation results.The proposed FxRSR method is mapped to hardware unit.This unit is implemented as a four-stage pipeline,achieving a throughput rate of 166.4 MHz on Xilinx Virtex-7 FPGA.Experiments show that the circuit throughput is improved,while saving ROM storage resources.But the scope of the proposed method is not as broad as Design A.Design A can not noly compute FxRSR of the real number,but also compute FxRSR of the complex number.