Research Of Color Image Compressive Sensing Based On FPGA

Compressing of image in traditional algorithm is happened after sampling, however, Compressive Sensing(CS) combine them together, therefore it avoids the dissipation of data from high-rate sampling, and it also alleviates the pressure of the subsequent. In the paper, a sort of modifications have been made. First, considering the data volume will be gigantic with a large scale of the to-be-processed image and the fluctuation in transform domain, the image is segmented into tiny blocks based on the local feature. Second, the Bayesian estimation is used in the algorithm. It provides posterior distribution of the parameter rather than point estimate, so it can optimize the data reconstruction adaptively. The experimental result indicates superior subjective effectiveness and a better performance of PSNR of the modified approach.CS will be realized in FPGA board DE2-115, and Quartus II was used to bring about the algorithm, D5 M to capture scene, SDRAM to store data, VGA to show the image. And because of the complexity of CS, the whole algorithm can not be accomplished only in Verilog which is for hardware driver and auxiliary data-processing, a soft-core is used, SOPC to build architecture, Nios II IDE to implement CS in C. And Matlab is used to simulate various kinds of modified algorithm. After CS was realized in VC++, we transplant the algorithm on hardware reasonably. At last, we use Signaltap to adjust the timing sequence to make the result optimum. The experiment on board show a good performance when compressing rate is 3:1.