Research On Video Background Modeling And Its Implementation Based On FPGA

Video background modeling is an important field of computer vision research, this research direction is the digital video stream processing and analysis system is a very important aspect, is the basis of video image processing related systems. Video background modeling correlation algorithm is relatively mature application in human-computer interaction, intelligent security, intelligent transportation and other scenes.Currently video background modeling algorithm GMM(Gaussian Mixture Model), ViBe(Visual Background Extractor) and a frame difference background subtraction model has been shown to have robust, has been widely used. However, in the traditional PC end processor running GMM and ViBe algorithms takes a lot of resources in dealing with high-resolution video streaming, conventional processor processor resources required will exponentially increase in consumption.Further, if the video background modeling algorithm which is implemented on FPGA(Field-Programmable Gate Array), that can significantly release the CPU's valuable resources, and reduce power consumption. Currently in FPGA platform video background modeling algorithm works mostly go beyond that, or placed in a dedicated application system a brief description, no internal function modules in depth.Through the study and research video background modeling algorithm hardware problem, this paper focus on solving the hardware design of video background modeling algorithm GMM, ViBe frame difference and background subtraction model, the main work is as follows:(1) To solve the problem of storage design and modeling process ViBe data throughput due to the high background caused by the problem of how to extract a cache neighborhood pixel values;(2) To solve the GMM hardware required process parameters fixed float switch problems;(3) Implementation of ViBe designed a simple pseudo-random number generator;(4) For the three background modeling algorithms to build FPGA testing platform, complete functional verification and collection of data through the serial communication and then processed using matlab algorithm to evaluate hardware-based post.