The Design And Implementation Of Storage System For MiniSys-1A

In this thesis the Storage System for MiniSys-1A system is designed. The purpose of the this project is to design and implement storage system to fulfill the requirements that help the system to work in a high speed as well as in a high performance, to expand the memory storage space and enhanced Minisys practicality, by using both Harvard and Von Neumann architecture, and in-depth study of the memory hierarchy in both side that from fast one to slow and from small one to big and try to decrease the speed gap between the MiniSys-1A CPU and memory, therefore the design of the memory consists of four level, level one cache (use Harvard Architecture, Instruction Cache and Data Cache), level tow cache (Von Neumann Architecture, Unified Cache, one cache for instruction and data), memory controller (main memory) and micro SDcard host controller which work as hard disk in the system. The whole system is based on Xilinx Vivado2013.4 suite design, and it is captured using Verilog Hardware description Language (HDL), configured to a FPGA target device belonging to the Artix7 family using Xilinx compiler, and simulated with Vivado Simulator.