Designand Implementation Of Beidou Receiver Baseband Processing

Beidou global navigation satellite system(BDS), which is a new generation of navigation system independently developed by China, with accurate positioning, velocity measurement and short message communication functions. This paper mainly studies the acquisition and tracking algorithm of beidou navigation receiver base-band. Furthermore, the paper gives a design and implement of base-band processing scheme based on FPGA. And this paper is mainly divided in the following aspects:1.This paper briefly describes the structure and characteristics of BDS's signal, as well as modulation process of the beidou pseudo random code and signal. Meanwhile, the paper gives introduction of the beidou receiver in light of working principle and structure. Finally, analyzes measurement errors from the perspective of satellite, transmitting process and receiver.2.The paper has made a detailed research and analysis in capturing and tracking B1 I signal. And has established mathematics model of signal receiving, by means of mathematics deduction, the author has analyzed time-domain sliding search and studied the parallel code phase search and parallel frequency of search algorithm on the basis of FFT. On the other hand, on the basis of MATLAB, the three kinds of capture algorithm simulation has been achieved, and the author endeavors to select a better parallel code phase capture algorithm as the basis of the forthcoming hardware implementation. Furthermore, this paper focuses on the signal tracking theory, analyzes structure and characteristics of the carrier tracking loop and pseudo random code tracking loop, and designs a loop dynamic performance and tracking precision tracking scheme of dynamic parameter adjustment as well as completes the tracking scheme based on MATLAB simulation.3. Finally, on the basis of the Xilinx ARM+FPGA chip, using verilog language to complete and to achieve the realization of FPGA in this paper. And put forward multi-channel multiplexing tracking design which effectively promoted the reuse rate of FPGA logic. And then, capturing and tracking of the key module design idea and implementation method have been detailed introduced. Under the help of Modelsim the function simulation of each module has been finished, and at the same time, given comprehensive logical resource consumption situation of each module. Finally, with the help of online logic analyzer Chipscope crawl internal key value of the signal lines, the performance of the design of base-band processing scheme was verified.