A Design And Implementation Of Inter-Thread Cache Interference Elimination Structure Based On Cache Partitioning

The traditional single-threaded embedded processor had the problems of random interrupt response latency and thread switching overhead under the management of multiple peripherals. Hardware multi-thread processor reduced the interrupt response latency and the thread switching overhead, due to the multiple hardware threads parallel executioa As the high speed memory, Cache has the advantages of software transparent and good average performance. The dynamic Cache partitioning method could promote system performance by suppressing the cross contamination of different hardware threads accessing the first level shard Cache.The pseudo LRU dynamic Cache partitioning method, for multi-level Cache structure, has the problems of complex partitioning and unable to suppress inappropriate partitioning in the first level Cache of hardware multi-thread processor. Complex partitioning could reduce the processor's execution efficiency and the processor time slice could be affected by inappropriate partitioning. The optimized dynamic Cache partitioning method was involved to solve those problems. Hit statistical analysis, based on binary tree replacement strategy was used in analysis circuit To reduce the partitioning complexity, the non-ergodic partitioning algorithm of low hardware overhead was adopted in analysis circuit and to suppress the inappropriate partitioning by partial partitioning method. The performance of system was improved eventually without reducing the reducing the interference elimination capability.The Mibench test shows that, by using the optimized dynamic Cache partitioning method in case of 4 threads executing in parallel, the interference miss rate was reduced from 50% to 15% and the IPC throughput rate and weighted speedup rate, compared to dynamic partitioning based on NRU replacement strategy, was increased by 11.8% and 15%respectively.