Design Of FSK/GFSK Baseband Circuit With Adjustable Data Rate

Nowadays, the wireless sensor network is applied more and more widely, while in different application environments the data rate is different. For example, the data rate in the real time voice transmission and other applications is higher, while the data rate in temperature, humidity and other information exchange applications is lower. So research on wireless digital baseband circuit with adjustable data rate is of great significance.Based on the function of the wireless communication chip, this thesis presents an improved digital baseband circuit structure. The digital baseband circuit mainly includes clock generating circuit, Gauss filter circuit, numberically controlled oscillator circuit, digital down converter circuit, decimation filter circuit, demodulation circuit, frequency offset compensation circuit and synchronization circuit. And the digital baseband circuit simulation, circuit design and test are completed. The clock generating circuit comprises a decimal frequency divider and two integer frequency dividers. The decimal frequency divider divides the system clock according to the data rate control word. The clock generating circuit generates clock to the digital baseband system. The digital receiving link receives the serial intermediate frequency signal from the Sigma-Delta ADC modulator. Firstly, complete the serial digital down conversion and then complete decimation filter process. Compared with parallel digital down conversion circuit, serial digital down conversion can reduce the circuit resource consumption. The ADC converts the analog signal to the digital data, at same time completes the data decimation and filtering process to reduce the data processing rate of subsequent digital circuit and reduce the power consumption. In the frequency offset compensation circuit, the current data subtracts the data delayed a cycle and get the modular. When the modular is greater than threshold, then calculate average value and realize frequency offset compensation. In the demodulation circuit, the CORDIC algorithm based on state machine is used to get the phase. The bit synchronization is realized by integrating the integral bit synchronization circuit. The Gauss filter is realized using the look up table structure. The FPGA verification platform is built to complete the verification of the baseband circuit system. The verification results show that the performance of the system meet the requirements. The baseband circuit was implemented in SMIC 0.18?m process and the chip area is 0.60mm. Chip test results show that the baseband circuit system is compatible with the modulation of Frequency Shift Keying and Gauss Frequency Shift Keying and the baseband circuit system can work normally with the transmission rate between lkbps and 500kbps. Under the AWGN with the SNR is 13.0dB, demodulation BER is within 0.1%, which meets the design requirements.