Design And Implementation Of LTE Physical Layer Based On SoC

As a development trend of future broadband wireless access(BWA), the LTE/SAE architecture is able to solve problems related to BWA for users and meet the demand generated by personal communications for broadband data services and multimedia businesses in the future. Therefore, it can be said that radio access network(RAN) is of great significance. For the network of private mobile communications, the development direction of future BWA technology is LTE. On account of technology-driven demands mentioned above, an LTE baseband processing platform applicable to the 6U VPX architecture should be developed based on the So C chip to lay a foundation for the development of follow-up wireless access devices and the wireless access function integration.The thesis mainly studies architecture and platform of So C as well as the design and implementation of LTE physical layer on such a platform in view of researches on the operating principle of this physical layer. Major works are presented as follows.1. Fulfill design and implementation of So C platform. Works including platform architecture design, So C design of selection, design of schematic diagram & PCB, So C related driver design, platform interface design and test & verification of So C foundation platform, etc. have been performed. Serdes interface of So C is extended through L2 Switch chip; as a result, the platform not only can implement BBU devices independently, but serve as an extended board which is integrated into other devices to realize the extension of wireless access function and improve its flexibility and applicability. In conformity with relevant Open VPX technical specifications, such a platform employs a form of 6U VPX plug-in card for the convenience of being integrated into the Open VPX architecture equipment.2. Fulfill design and implementation of LTE physical layer based on So C platform. Both task scheduling mechanism and task allocation mechanism are designed on the basis of So C chip architecture. In addition, combining the So C chip architecture, the process procedure design of down and up links is conducted based on a Matlab simulation of links on the LTE physical layer. With an aim to improve the efficiency of MAC-PHY interface communication and based on the FAPI interface, time relation design and MAC-PHY interface design are carried out by means of large message. Therefore, frequent information interactions between layers are reduced to improve their efficiencies; and in addition to satisfying functional performances, design complexity drops at the same time.3. Fulfill the functional test of LTE physical layer on So C platform. A method of driving test is adopted to test the required time of PUSCH, PUCCH, PRACH and physical layer processing on the So C platform. After the comparison of results between testing and Matlab simulation, design of the channel link at the physical layer is verified to be rational.