An SoC FPGA-based Processing System For High Dynamic Range Real-time Video

With the development of ages, the higher image quality requirement is needed. Under the cases of non-uniform intensity, the quality of low-dynamic-range(LDR) images are usually low due to the loss of detail. Because high-dynamic-range(HDR) images have greater dynamic range, a better reality scene can be shown. Nowadays, a growing number of CMOS image sensor with high-dynamic-range mode, the video processing technology for high-dynamic-range image has been increasingly concerned. Compared with ordinary video, high-dynamic-range video has a larger amount of data, so the requirement for the processing ability of system is higher, traditional sequential processing engine such as DSP must be replaced by FPGA, which has higher processing ability for its parallelism. Although the parallelism and programmability of FPGA can accelerate the image processing algorithms, this pure hardware image processing platform has the disadvantage of long secondary development cycle, non-flexibility and poor controllability. By integrating the ARM core and FPGA on the same chip, So C FPGA provides a good solution to the pure FPGA system problems. An So C FPGA-based video processing system combines the flexibility and controllability of So C System and the programmability and parallelism of FPGA system, more and more applications in video image processing field has been found.The design of an So C FPGA-based high-dynamic-range video processing system includes two parts: hardware system design and software program design. Hardware system consists of video capture, pre-processing, tone mapping and display. According to the system design requirement, this paper first complete the high-dynamic-range video capture module, I2 C controller module, image pre-processing module, color space conversion module, tone mapping module and image display module by using Verilog HDL. And then these modules are encapsulated into IP core based on Avalon protocol specification. Finally, integrating these IP cores with ARM core in Qsys to from a high-dynamic-range processing hardware system that has ARM architecture. Software program implement the image sensor initialization and exposure control using C language.At the last of this paper, high-dynamic range video processing system is verified on hardware. First, connecting the terasic's DE1-So C development board and the Aptina's MT9M034 CMOS image sensor with the display device to form a display system. And then, downloading the hardware system architecture configuration file to the development board. Finally, run the software program in the Linux system to complete the verifying work. After verifying the high-dynamic range video processing system based on So C FPGA, the display can real-time show the image data captured from the image sensor.