HDL Code Performance Valuation And PAITS Optimization

The control of HDL source code quality is a significant factor for improving the quality of So C/ASIC chip acts as an important process in its quality assurance system. If a design can't reach the optimization target after retiming, its code should be changed and compiled again, a time-consuming and complex job. Helping accomplish this iterative loop can also shorten the period of developing and increase the design efficiency.In order to develop a chip design in a rapid and highly efficient manner, it is certainly worth detecting flaws at an early stage of the design or reducing each design iteration. In this paper, two methods of shortening the period of developing are studied, which are the digital circuit parallel all- indegree topological-sort optimization algorithm and static timing analysis for digital circuit based on RTL- level code. The main study and conclusive results are as follows:HDL code static timing analysis is presented to develop HDL code with better timing performance. This analysis should be implemented after simulation and before the logical synthesis. A brief basic analysis of the timing of a circuit is given based on the circuit structure model and gate delay model. This paper models the timing path in a circuit using a tree structure. Vertices with inputs and outputs represent each timing path; forward directed edges represent input signals; reverse directed edges represent output signals or the variables being assigned; the weight of vertices represents the delay of paths. And the delay of each path in circuit can be predicted with its HDL code modeled by this method. Therefore, a designer can get the critical path and its delay and estimate whether the circuit satisfy the target frequency. Results show that this method can find the critical path of the circuit and the relative error of predicting delay is within 30% compared with STA.If a design can't reach the optimization target after retiming, its code should be changed and compiled again. To solve this problem, parallel all- indegree topological-sort algorithm(PAITS) is presented in this paper based on the principle of topological-sort and the circuit parallel characteristic. Based on the directed graph method, the proposed optimization algorithm analyzes the circuit. The circuit is sorted by PATIS, and the position which the pipelines in the circuit can select and the corresponding information can be obtained. Select the proper position to insert the pipeline by rewriting the netlist, and achieve the circuit optimization without rewriting the RTL code. The time complexity of PAITS O(f?|V|+|E|) is smaller than that of the FEAS O(|V|?|E|), and the symbol f represents the fanout of a circuit. Moreover, experimental results also demonstrate a significant improvement over retiming algorithms in area by 20-40% with the same registers stage in.