The Design And Implementation Of 3D-NoC Mapping Algorithm Based On Chaotic Particle Swarm

With the rapid development of the embedded field, System on chip fell into its bottleneck. The related researchers put forward the concept of computer network into the field of embedded system design, so the network on chip came into being. Make the separation of network nodes and resource nodes, based on the global asynchronous and local synchronization and with the routing strategy and switching technology, network on chip show superior performance in power consumption and delay performance to meet the development needs of embedded system and become the big direction of the design for embedded system. In order to display the advantages of the network on chip in power consumption and delay, it need a reasonable and efficient mapping algorithm. The mapping algorithm of 3D network on chip is a NP complete problem. Many intelligent algorithms are applied to the mapping problem of the network on chip. However, there are still some problems, which include low efficiency, mapping unreasonable, not considering power consumption and delay together. As a result, a further research on the mapping strategy of the three dimensional network is needed.In this paper, we do some research on the mapping algorithm of 3D network. Firstly, it introduced the topology of the network, the network platform, the routing algorithm, the related mapping theory and the power consumption and delay model.Secondly,it respectively analyzed the performance of the mapping algorithm based on genetic algorithm, ant colony optimization and particle swarm optimization.Lastly, in view of the shortcomings of genetic algorithm, ant colony algorithm and particle swarm optimization, this paper designs and implements a mapping algorithm based on chaos particle swarm optimization, which is mainly divided into two stages. In the first phase, according to the DAG, the priority value of each task is calculated by the formula. Owing to the priority value of the tasks in the critical path is the maximum, the critical tasks are mapped firstly, which can reduce the total time of the tasks. In the second phase, using the results of task mapped in the first phase, the algorithm make use of chaotic particle swarm optimization and power-delay model to generate approximate optimal mapping scheme.Through the TGFF(Task Graphs For Free), sets of task are generated, and the algorithm parameters are set up. Using Java software Eclipse, the three mapping algorithms are implemented respectively based on genetic algorithm, ant colony algorithm and chaotic particle swarm. According to the mapping algorithm, the mapping algorithm is mapped to the kernel, then the kernel is mapped to the network node. The simulation results show that the algorithm based on chaotic particle swarm has the better power consumption, delay performance and convergence effect compared with the genetic algorithm and ant colony algorithm.The design and simulation of the mapping algorithm of the 3D-Network on chip are completed in this paper. This paper has some reference value for the research of the mapping algorithm of the 3D- Network on chip.