Design On The Nanoelectronic Dielectric Film Fabrication Processes And Device Characteristics

With the rapid development of very large scale integrated circuits, the feature size of MOSFET continues to reduce, this leads to the demand of higher capacitance density for both MIM capacitors and MOS transistors. The conventional homopolar dielectrics such as SiO2 and Si3N4 can no long meet the new requirements. With this connection, high dielectric constant (high-k) film was proposed to replace the conventional dielectric. Because of the larger physical thickness, the direct tunneling effect can be suppressed effectively and the capacitance density can be enhanced. The research aims at studying some fabrication issues related to the deposition of high-k films so as to improve the fabrication process and device characteristics of future nanoelectronic devices.In the first part of this thesis, we investigate the process for depositing some high-k devices such as Ta2O5, Al2O3 to be used in integrated MIM capacitors. The films were deposited with CVD and ALD. The cross-section and morphologies of the films were characterized, respectively, with TEM and AFM. We found that the leakage currents of the films were affected by the surface roughness. Asymmetric ?-? curves are registered for different polarity biases. The characteristics can be improved by smoothing the surface using ZnO. Different conduction mechanisms in the films were identified based on the temperature dependent current-voltage characteristics.The second piece of work is on the future MOS gate dielectrics. We focus on the method for oxygen chemical potential control to reduce the oxygen vacancy level on La2O3 films. Firstly, we investigated the chemical and compositional variations of La2O3 thin film on the silicon substrate during rapid thermal annealing by using ARXPS measurements. Results show that thermal annealing at temperatures above 500? would result in the incorporation of substrate Si atoms deep into the bulk of the film and forming silicate phases both at the interface and in the bulk, which deteriorates the performance of the dielectric film. By using CeO2/La2O3 stacked structure, the electrical properties can be improved. This work presents a detailed study on the chemical composition and bond structures at different depths by using XPS measurement. By analyzing the Ce 3d, La 3d, Si 2s, and O 1s photoemission spectra at different depths, we found that La atoms can diffuse into the CeO2 layer and a cerium-lanthanum complex oxide was formed in between the CeO2 and La2O3 films. Ce3+ and Ce4+ states always coexist in the as-deposited CeO2 film. In addition, as compared with the single layer La2O3 sample, the CeO2/La2O3 stack exhibits a larger extent of silicon oxidation at the La2O3/Si interface. For the CeO2/La2O3 gate stack, the out-diffused lanthanum atoms can promote the reduction of CeO2 which produce more atomic oxygen. These observations provide useful information for the process and characteristic optimization of the high-k gate dielectric film based on CeO2-La2O3 structure.