A Research On The Simulation Method Of Probability Circuit Base On FPGA

With the development of IC industry, the processing speed and energy consumption of microchip are both increasing rapidly. As the feature size step into nanoscale, the influence on electrical properties of CMOS devices caused by all kinds of internal interference factors cannot be ignored anymore. At the same time, as the popularization of all kinds of electronic products is getting faster and faster, people have higher expectation on the hardware performance as well as the decrease of power consumption. Researchers proposed the concept of PCMOS to solve these problems. In order to apply PCMOS in practice, carry on the simulation modeling is the first step. FPGA-based simulations implement the circuit on the FPGA which enables a large simulation speed-up.In this article, we first introduce the basic characteristics of probability circuit, then simulate and analyze the simulation speed of FPGA-based simulations. Then we introduce a single level FPGA-based fault simulation algorithm, simulate and analyze its circuit overhead. Aiming at the existing problem of the single level algorithm, we put forward a new multilevel simulation algorithm, simulate and analyze the new algorithm. Simulation results show that the new algorithm can reduce the circuit overhead effectively.We also do a research aiming at the algorithm about adjusting the error probability of the probability element. We introduce, analyze and simulate a three step matrix-constructing algorithm, aiming at the existing problem, a new algorithm based on steepest descent method and dichotomy is proposed. The new algorithm can make the adjustment process more organized and directional, and improve the overall simulation speed.