Study And Design Of A Coarse-fine Time-to-Digital Converter

With the rapid development of technology,a higher requirement for precision time quantitation is needed,but traditional time quantization method is difficult to meet the actual demand in many applications.Therefore,Time to Digital converter(TDC)emerges to measure a very short time interval,converting the time signal to a digital signal.TDC is widely used in the field of time of flight measurement in high energy physics experiment,positron emission tomography in medical science,satellite synchronous,radar ranging and laser ranging,etc.As the core unit of time measurement,the performance of TDC directly decides the final measure resolution.Thus the research on wide time range and high precision TDC is of great theoretical and practical significance.Field Programmable Gate Array(FPGA)based TDC and Application Specific Integrated Circuit(ASIC)based TDC are the two mainstreams to design a time to digital converter.ASIC based TDC is chosen in this paper for the high resolution it can achieve.Based on the research of TDC with different structures,a coarse-fine TDC is presented in this paper,the proposed TDC has both high resolution and wide dynamic range.First of all,this paper introduced the principle of TDC with different structures,and explained the overall framework of the designed coarse-fine TDC.Then,the detail of every part is explained: the coarse level used a loop counter at the end of delay line,a special delay cell and a symmetrical DFF are designed in this part,so that it can achieve wide dynamic range and avoid the error of different transmission paths,the coarse level has a resolution of 4ns.The fine level utilized a vernier delay line based on dual-DLL structure,while the core parts of DLL,PFD,CP,edge detector,and VCDL were especially designed in this part.In order to improve the performance of DLL,this paper also designed a new start-control circuit.The fine level has a quantization step of 8ps.In addition,a middle level used a typical delay line is added to reduce the chip area.The simulation result and error analysis is presented at the end of this paper.The design and simulation are based on Cadence Spectre software using 0.5?m CMOS process.The simulation results show: the coarse level has the quantization step of 4ns and the dynamic range of 1.2?s,the middle level has the quantization step of 0.25 ns and the dynamic range of 4ns,the fine level can achieve the resolution of 8ps and the dynamic range of 0.25 ns.The time of control voltage from DLL to achieve a stable state are 460.9ns for the fast loop and 582.6ns for the slow loop,and the stable control voltages are 1.798 V for the fast delay line and 1.59 V for the slow one.The circuit works well under the reference clock of 125 MHz.The simulation result indicates that the system meet the design objects.