The Design Of Power Quality Detection Equipment And The Implementation Of Algorithm Based On ZYNQ

With the increasing demand for power quality detection devices in power system,the research and design of these devices become more and more important.This paper takes the ZYNQ series FPGA chip of XILINX company as the main part to design a new architecture of power quality detection system.Through the analysis of the current situation of the development of the domestic and foreign equipment,it is not difficult to find that the performance of the domestic electric power detection device,whether it is a product or a single product,is lagging behind the developed countries.At present,the majority of manufacturers in the market are using the DSP chip as the main chip for data processing.With the development of FPGA and its unique advantages in parallel operation,FPGA has gradually replaced the DSP in many fields.Through the analysis of the content and standards of power quality detection,this paper presents the system design scheme and hardware circuit topology of power quality detection system.In the general AD acquisition system,the frequency of the sampled signal itself will fluctuate.The fluctuation of this kind of signal can cause the problem of non-synchronous sampling,which makes the FFT(or DFT)result in a certain spectrum leakage.In general practice,people use zero crossing detection or windowing algorithm to solve this problem.Because there are many problems in the zero crossing detection,this paper mainly uses the windowing algorithm to improve the accuracy of data analysis.Through the analysis of the different effect of the window function with MATLAB,this article finally chooses the Hanning window in the design.Due to the need of using a large number of data in the process of window algorithm,this paper mainly uses XILINX's latest ARM+FPGA architecture to achieve the fast calculation of a large number of data.The architecture makes full use of the powerful and fast computing power of the FPGA chip,combining the flexibility of ARM.In the design of FPGA(PL),this paper combines the IP kernel of VIVADO and the IP kernel written by Verilog to realize the accurate calculation and analysis of raw data.Finally,the final result is run and analyzed on the peripheral interface of ARM(PS)by calling the library function and writing the C language code.