Design Of Hdl Code Checking Software For Aerospace Model FPGA

With the FPGA(Field-Programming Gate Arrays)becoming more and more prevailing in the aerospace nowadays,the code quality which is written on HDL(Hardware Description Language)is becoming incresingly critical to the system safety of the aerospace equipments.In China,China Aero Science and Industry Corporation(CASIC)has proposed a HDL coding standard “Q/WE1117-2014 HDL coding standard for China Aerospace Science and Industry Corporation’s FPGA designs” which is aimed at spacifying the coding style and improving the code quality of FPGA designs in the aerospace programs.However,it would take a lot of manual effort and time to perform code checking while the FPGA designs are becomming more and more complex.To provide efficient code checking on the early stage,this paper design and develop a rule-based Verilog HDL code checking software based on the Q/WE1117-2014 standard.Base on the research of the Q/WE1117-2014 standard and the analysis of the software’s requirements,the overall architecture of the rule-based code checking software is proposed.The software is composed of software configuration and manager tool,Verilog HDL preprocessor,Verilog HDL compiler and rule checking manager with its checker library.The software configuration and manager tool is the interface of the entire software and provides MDI(Multiple Document Interface)style source code editor,code file list entablising and mantainning function,rule configuration and management fucntion,checking execution function,execution process display and checking results display windows.This tool is designed based on the Notepad++ open source editor.Verilog HDL preprocessor and compiler are used to translate the source code into a semantic model called AST(Abstract Syntax Tree).Based on the study and the analysis of lexical defination and grammars of Verilog HDL,the Verilog HDL preprocessor and compiler are implemented through developing the flex lexical file and bison grammar file.Moreover,an implementation of AST is proposed。The checking function manager is used to perform code checking by calling the appropriate checking funtions in the checker library according to the configuration file which is maintained by software configuration and manager tool.The checker library is used to store the checking functions which are actually C/C++ function realizing verification of apporpriate rule.The checker library is encapsulated as DLL(Dynamic Link Library).Moreover,all the checking functions observe a uniform function interface.Thus,any new checking function can be added to the library easily.To perform code checking base on the Q/WE1117-2014 standard,many code checking functions are designed and implemented.Finally,the Verilog HDL code from practical FPGA projects and the Verilog HDL code which are developed to test all the checking functions are used to verify the function of the software.The result shows that the software operates stably and can find the violations in the code correctly,which have met the design demand.