Development Of High Precision Pulse Delay Adjustable Circuit System For Ultra High Speed Photography

The current high-speed framing camera in the aviation,military,scientific research and other fields have a wide range of applications,it can be used to capture the momentary state of the object,such as the missile trajectory in the trajectory.With the continuous development of science and technology,more extreme conditions for the application of the scene for the framing camera performance requirements are also rising,the future of the framing camera must move toward high-speed,high precision,portable direction.For the framing camera,the core imaging device for ultra-high-speed exposure is an ICCD camera(ultra-fast gated)consisting of an adjustable pulse delay circuit.Its performance directly determines the performance of the framing camera.A high-speed,high-precision pulse delay adjustable circuit for the development of framing camera technology is extremely important.This paper introduces several design schemes of pulse delay adjustable circuit.After analyzing the advantages and disadvantages of each scheme,the design scheme of analog delay chip and digital delay is used to solve the problem of signal jitter,and to achieve a maximum 10 ms delay,10 ms pulse width,and 1ns delay resolution.Using FPGA to achieve the 5ns delay resolution,and connect with analog delay,through the second delay,improve the delay resolution.When the input signal enters the FPGA,it will first be synchronized by the clock,this will produce a random 0 ~ 5ns clock synchronization error,which will lead to the jitter problem between output signal and the input signal.In order to eliminate jitter,this paper designed a counter chip and analog delay chip signal jitter compensation circuit,the counter chip to measure the clock synchronization error,and then through the analog delay chip to compensate.In order to achieve adjustable pulse width,this paper uses two different delayed signals,the delay difference is the desired pulse width,and then the two signals after the logical operation are combined into one output signal.The design uses STM32F103 series microcontroller as the core controller,communicating with PC-side host computer,and then send the configuration delay data to the FPGA.After the design is completed,the resolution,stability and inherent delay of the pulse delay adjustable circuit are tested and analyzed.The innovation of this scheme lies in the proposed signal jitter compensation circuit combined with the counter chip and the analog delay chip.The scheme is simple and easy to operate,and the resolution is high,which can effectively control the signal jitter within 1ns.At the same time,a simple and effective design scheme with adjustable pulse width is proposed.After the completion of the pulse delay adjustable circuit design,carried out various aspects of the test,the system modules running stable,and to meet the design requirements,the overall design is feasible.The pulse delay adjustable circuit is low cost,small size,and the delay resolution is high,the delay range is large,the signal jitter is small,the signal output is stable,and it has been used in practical scientific research,and has wide application prospect and use value.