Research And Implementation Of Miniaturization Rendezvous And Docking Radar Tracking Algorithm

The Direct Sequence Spread Spectrum signal tracking is the key to the Miniaturization Rendezvous and Docking Radar tracking algorithm, and the carrier tracking and the pseudo-code tracking are the cores. This paper studies tracking algorithm for Direct Sequence Spread Spectrum signal, and further researches the tracking loop structure and optimized program to achieve the miniaturization of the Rendezvous and Docking Radar tracking algorithm. First, this paper explains the principle of the Rendezvous and Docking Radar tracking algorithm, and then describes the common tracking techniques: the carrier tracking and the pseudo-code tracking, Finally, research and miniaturization rendezvous radar tracking algorithms.The carrier tracking loop comprises Frequency-Locked Loop(FLL) and Phase-Locked Loop(PLL). First, the paper analyzes and compares the common discriminator methods and then give the system function according to the loop filter model, and finally investigate the effects of parameters on the loop performance of the loop. The introduction of Delay-Locked Loop(DLL) focuses on the working principle, the methods for discriminator, the loop filter and carrier assisting. The paper gives the analysis of measurement error to PLL, FLL and DLL.The research and implementation of the Miniaturization Rendezvous and Docking Radar tracking algorithm focus on the optimization of the DLL, carrier tracking loop and Circuit coupling. For the Delay-Locked Loop(DLL), the paper gives the optimized design of the methods for discriminator, correlation interval and loop bandwidth, and analyzes the different influences on tracking performance through the simulation. The paper study on mixed tracking loop by combining Second-order FLL and Third-order PLL. Because the Second-order FLL has better dynamic tracking capability and the Third-order PLL has higher thermal noise tracking accuracy. Simulation compares the tracking performance between the structure of FLL serial assisted PLL and the structure of FLL parallel assisted PLL. The multiple-using structure of circuit reduces the use of resources by time division multiplexing manner. This section presents a realization structure and design, and the FPGA design verify the correctness of the miniaturized design. The end of this paper presents the summary and the prospects of following research.