Improvement Of Chaotic Map Based On Anti Reverse Iteration And FPGA Implementation Of High Order Chaotic Sequences

With the progress of science and technology, the height of growth of mobile communications technology, the traditional pseudo random sequence has shown the sequence length, the number of limited, complexity is not high, can not meet the needs of the existing. Chaotic sequences by iteration of nonlinear system, with highly to the initial value sensitivity, convergence is bounded, ideal correlation and other excellent properties, the more and more by the majority of scholars pay close attention to and study, used in the field of communication with a broad development space.Logistic chaotic mapping dynamic system only one control parameter items and small range of chaotic interval, application in the network communication security field will small key space to generate the key stream sequence security flaws, also due to multiple iteration of linear transformation, making the chaotic mapping reverse iteration to obtain the initial value of the possibility of a larger, which greatly limits its application. According to the above analysis, this thesis in the conversion process according to the value of the Logistic chaotic map requirements into sine function control constructed a modified Logistic chaotic mapping, the mapping is in a chaotic state in the range of fractal factor more wide and improve the non linear complexity, anti reverse iteration crack capacity is increased. Through calculation and simulation analysis of bifurcation diagram and Lyapunov exponent, sensitivity to initial conditions, correlation, balance, run length characteristics, power spectrum density and transmission capacity etc.. The results show that the improved mapping performance is good, through the anti reverse iteration test more applicable in electronic commerce, data encryption, digital watermarking and secret communication applications.FPGA system in the process of dealing with complex floating point multiplication operation, there will be the call of the circuit resources increased exponentially with the increase in the amount of calculation results, it is easy to cause the system to collapse. This kind of problem in the digital realization of Chebyshev chaotic map is particularly prominent, with the order so that the increase of the Chebyshev spread spectrum sequence performance more and more excellent, but usually these sequences generated only in the integrated with rich resources of more expensive hardware circuit can be realized. Therefore, how to minimize the resources and costs to achieve a higher order Chebyshev digital sequence is very meaningful. For the first time, a Chebyshev mapping iterative algorithm is proposed for the parallel call of FPGA circuit resources, and the high order Chebyshev polynomials are optimized for the optimization of the deformation. On the one hand through reduce the highest index of polynomial initial value to reduce the iterative process in a lot of index operations, on the other hand try to dissolve into polynomial and the same value index items, mostly in the form. This transformation is conducive to the allocation of FPGA resources planning to large complex unit and the use of low order exponent of the corresponding high speed operation module instead of the original high order exponent of the corresponding low speed operation module, improve the parallel processing capabilities of the hardware circuit, greatly reduce the hardware circuit computing resources share, get more excellent performance of Chebyshev chaotic digital sequences in the low cost of hardware circuit. Finally, the performance of the obtained sequence is analyzed. The results show that the high order Chebyshev chaotic sequence has the excellent characteristics of the pseudo-random sequence.These work has certain reference value for the research and development of spread spectrum communication.