Hardware Design Of Inter-frame Predicting Module In SVAC Encoder

《Technical specification of surveillance video and audio coding》 (SVAC) has been launched in China with the contribution of all brainstorms of our own country, in which the surveillance video and audio encoding and decoding methods and steps are described and stipulated. It has brought brilliant advantages to compress and transmit video data using protocol of SVAC, including saving great number of patent fee. In this paper, hardware design and implementation of inter prediction using SVAC has been depicted and discussed.After elaborate analyzing the basic principle and key technologies in SVAC, the article deals with the issues of hardware algorithm of modules of frame-dividing, integer-pixel motion estimation, sub-pixel interpolation, process of B-frame, extraction of region-of-interest, etc. Hardware design is based on the thesis named above, together with character of surveillance and system demands.An improved delaminating inter-pixel searching method has been put forward to fit the design. It starts in the same line where the predicted motion vector lies. Every other pixel is taken into consideration, together with four pixel holding the distance of ’1’ to the zero point. An 8x8 sub-block is matched in the searching area of 24x24 using parallel pipeline. Values of MV and SAD are then compared in the judging module, according to different priorities based on distances to the zero point. A highly parallel sub-pixel motion estimation has been applied to the design, in applying of the symmetry of fractional pixels. Cost optimization of eight 1/2-sub-pixel and sixteen 1/4-sub-pixel positions is acquired through three times of interpolations and twice comparisons. The algorithm and hardware architecture of bi-directional prediction is discussed in this paper, a flowchart on prediction mode judging is given. Depending on the threshold of MV and SAD, module of extraction of region-of-interest is added into the design as well, which can provide the interface for quality variable encoding.The RTL design of the SVAC inter prediction module is compromised in Verilog hardware-design-language, compiled and synthesized under the circumstances of Quartus II 13.0. The target fitting board is Altera Cyclone III EP3C120F780C8. Functional simulating verification has been launched in Modelsim 10.0a. Results show that the design is in accurate time sequence and is working properly, which can fully meet the needs of high-definition surveillant video encoding.