Design And Implementation Of AXI Port Based On C-RAN Digital Front-end

Now, the mobile operators face a strong competitive environment, as the cost of building the Radio Access Network(RAN) and power consumption keep high and grow up while the revenue remains relatively low. At the same time the mobile Internet traffic develop rapidly, while the ARPU(Average Revenue Per User) has remained flat or even declining. In order to achieve profitability and keep sustainable development, a new network called C-RAN was first proposed by the China Mobile Academy, which consists of Centralized signal processing, Cooperative radio, and real-time Cloud infrastructure RAN was proposed. C-RAN architecture can reduce operators’ costs, and increase users capacity.It would be the future direction of the radio access network development. This novel network architecture can solve the challenges that mobile operator faces and makes them more competitive.To start with, the AXI4 bus protocol and important features of AXI bus would be analyzed in this thesis, then its channel structure, as well as read and write timing handshake. This thesis also researchs on the overall architecture of C-RAN, and analyzes the data flow of C-RAN digital front-end board. The data flow of digital front-end board respectively comprises an uplink data to the server and downlink data from server to digital front-end board, data flow of communication accelerator modules and data carrier modules. The three main sub-module bandwidth needs of data flow are analyzed, wherein the equalizer sub-module communication bandwidth requirements accelerator reached 9.2285 Gbps, which is the largest bandwidth demand of the module.Secondly, according to the inter-digital front-end module board data bandwidth requirements, AXI Master Port and Slave Port are developed to meet the inter-digital front-end module board data transfer.The data bus width of AXI4 bus is designed as 256 bits, and reach the maximum burst length of AXI bus protocol. Dued to the AXI bus protocol channel characteristics, Master Port and Slave Port read/write channel would be designed in separate, each channel using the state machine to control source, send destination data, and use asynchronous FIFO form data width conversion and clock domain conversion.Then, use the Modelsim simulation software of Mentor Graphics to simulate AXI Master Port and Slave Port. In the end, the Master Port and Slave port will be tested on the digital front panel board Stratix V series chips of Altera Corporation, and use SignalTap tool of QuartusII software to crawl waveform observation. After being synthesized and layouted, the Master Port and Slave Port maximum clock frequency have reached 313.38 MHz and 371.06 MHz respectively. It proves that the design of the AXI Master Port and Slave Port meet the needs of C-RAN internal digital front-end module for data transmission.