| Image edge feature is one of the most important image low-level features, which is the guarantee of accuracy operation of upper algorithm. With the development of artificial hardware, it is practical to realize the algorithm of image edge detection in hardware.The algorithm of Sobel can be ported to hardware for many algorithms of image edge detection are researched. Sobel Hardware Accelerator is designed and simulated on the Modelsim. To begin with, six algorithms of image edge detection are analyzed. The algorithm of Sobel is used to realize in Verilog, because it’s quality and speed is better than others. The convolution of Sobel is designed with pipeline for improving efficiency. The design of data flows and control flows are included in the design of Sobel Hardware Accelerator. The data flow includes the start of the pipeline, the stability of the pipeline and the discharge of the pipeline. Finite-state machine which includes Moore state machine and Mealy state machine is the core of the control flow. According to functional modules, Sobel Hardware Accelerator is divided into four modules:interface, the module of calculation, address generator and finite-state machine.Last, the simulation of Sobel Hardware Accelerator and simulate outcome are studied on the Modelsim. A testbench is established for running Sobel Hardware Accelerator. The testbench includes CPU, arbiter, memory and Sobel Hardware Accelerator.The analytical results of CPU, arbiter, memory and Sobel Hardware Accelerator are in concordance with theory. A complete picture is tested by the testbench for verifying Sobel Hardware Accelerator. The testbench outputs data which can generate an edge picture. The edge picture proves the algorithm of Sobel is ported successfully. That is the reference of porting to FPGA. |
