Research On Key Technology Of Elliptic Curve Cryptography Processor

Elliptic curve cryptography(ECC) processor is an important way to achieve elliptic curve cryptography, and key technology of elliptic curve cryptography processor has importantly theoretical and practical significance. Our team has implemented an ECC processor for dual-domain within a 576-bit elliptic curve length. It is of outstanding performance in the similar designs, but has huge resource consumption. This paper based on the ECC processor, carries out studies on two aspects of elliptic curve cryptography processor, architecture and operation unit, to optimize performance and resource proportion.Thesis has studied scheduling features of point adding and point doubling in affine coordinates and establishes a scheduling optimization model of point adding and point doubling. By solving mathematical modeling, we get optimization results of scheduling point adding and point doubling. We also get a heterogeneous dual-way paralleling architecture of arithmetic unit configuration. Based on this study and combining with the elliptic curve cryptography processing features, this paper propose an instruction execution mode called VLIW-matrix, which come from the VLIW instruction structure and absorb Super Scalar architecture thought, execution out of order. Then, we design a hierarchical clustered storage structure for VLIW-matrix including clustered register file and vector structure memory, effectively improving the efficiency of data scheduling.This paper studies designing arithmetic units of ECC processor. First, we decide to optimize modular division operation in affine coordinates. Through improving algorithm, we propose a double-bit scanning modular division algorithm. Then we realize the high-speed modular division unit. We also improve modular multiplication to obtain double-bit scanning modular multiplication algorithm. Modular multiplication unit is designed based on an adder structure, which can multiplex modular division unit structure, and can be compatible for modular addition and subtraction. So we achieve a unified functional unit based on modular division unit, which could realize all finite field operations. Theoretical and experimental evaluation show that, based on our double-bit modular division and modular multiplication unit, point adding and point doubling in affine coordinates could reach the same performance, compared with that in projection coordinates. And the functional unit resources are greatly reduced.Finally, this paper implements an ECC processor based on the architecture and arithmetic functional units we proposed. This paper also makes verification and analyzes the performance of the system. The results show that the design optimization of ECC processor has reached the goal of maintaining high performance and reducing resources. Our work provides new ideas and key technology to design optimized ECC processors.