Design And Implementation Of Harris Corner Image Registration System Based On FPGA

The image registration is to align two or more images of the same target in space and is also known as image matching or image correlation. The technique is widely used in the aspects of remote sensing, medical, military, environmental monitoring, disaster prevention, etc. Existing embedded systems mostly make use of software to achieve the core algorithm of image registration. Due to the huge amount of data and computing capacity, performance and processing speed are generally not ideal. After referring to a large amount of relevant literature and periodical, this thesis presents a kind of design of the image registration system based on FPGA, taking advantage of its parallel processing mechanism and powerful computing capabilities to improve processing speed and performance of the system.This system uses Altera DE2-115 Development Platform. FPGA reads grayscale data of the two images from external SRAM and outputs the transformation matrix between the two images after processing. The system consists of four main parts: SOPC system overall design, corner extraction IP core design, Harris corner extraction module design, and corner registration software design. The SOPC system overall design is to build SOPC system in Qsys and to complete the main program of NIOS Ⅱ processor. Corner extraction IP core is mounted on the Avalon bus, including Avalon bus controller, SRAM controller, corner memory, and corner extraction module. Harris corner extraction module implements corner extraction. The process of corner extraction is pipelined and the process of left and right images is paralleled which greatly improved the corner extraction speed. The maximum frequency is up to 100MHz. When the pipeline is full, the calculation of a pixel can be completed within one clock cycle. Corner registration software consists of corner registration pretreatment, corner coarse registration, and corner RANSAC registration. The parameters of transformation matrix are solved by means of Gaussian elimination. PC software is also designed to see and investigate the results.Tests show that, NIOS Ⅱ processor and corner extraction IP core can be able to run at the clock frequency of 100 MHz stably in Cyclone IV EP4CE115 FPGA. The corner extraction of two 512 × 512 images can be completed within 2.622 milliseconds, which greatly improves the speed in comparison with corner extraction algorithm based on general-purpose processor. Then corner registration and calculation of the transformation matrix is completed by software. System achieves the desired functionality, with high speed, accuracy and portability, and with a wide range of applications.