Research Of Process-level Redundant Static Binding And Dynamic Binding Mechanism Based On Domestic Multicore Processor

Fault-tolerant technology is a technology for guaranteeing the correct execution of the program in some high-reliability environments. While the program runs in computer, many different types of failures may occur. How to guarantee the correct execution of the program is a hot spots.The multi-core processor is the tendency of today’s processors. Loongson3 chip family is very representative of the domestic multi-core processor chips. How to enhance the performance of domestic multi-core processors in fault-tolerant and how to make full use of the hardware resources of domestic multi-core processors has important significance. In fault-tolerant technology of multi-core processors,according to the usage of processor core, it can be divided into static binding and dynamic binding. Static binding technology is specifying a specific processor cores before running redundancy process, and dynamic binding needs to take the current actual operating conditions into account when determining which cores to run redundancy process.Static binding and dynamic binding of the redundancy process are achieved and the function of fault detection based on multi-modular redundancy is completed in this paper. In traditional binding methods, the communication between different redundancy processes need a dedicated communication channel or buffer queue,which must be designed before the chip manufactured. The functionality of fault detection at the kernel level is achieved in this paper. The communication and comparing of redundancy processes is transferred to the system call. This fault detection method which uses software, not only can effectively detect the failure occurring in the running of process, but low cost and short the development cycle.Finally, we implements the experiment which uses the method of static binding and dynamic binding for redundant process and successfully detects the injected faults,then analyzes the impact of two methods on the system performance. The result shows that the influences on the performance of the system is acceptable. The work of this paper not only providing some reference for multi-core processors in the software layer fault-tolerant, but also providing some theoretical reference for reliability design of domestic multi-core processors.