Circuit Implementation Of A Linear Combination Type FRFT

In recent years, digital signal processing technology has been developed rapidly. In the field of digital signal processing, the traditional Fourier transform has been developed relatively mature. But with the ever-expanding variety of applied signals, Fourier transform gradually revealed its limitations on dealing with non-stationary signals. To address the drawback, new signal analysis theory, such as wavelet transform, Gabor transform, Wigner distribution and fractional Fourier transform, have been brought one after another. As a generalized form of the Fourier transform, fractional Fourier transform can well express the signal’s local time domain and frequency domain characteristics, and thus favored by many researchers. In this thesis, some discrete fractional Fourier transform algorithms are studied and analyzed, and one is designed and implemented based on FPGA.Firstly, this thesis gives a brief overview of the definition and nature of the fractional Fourier transform. And then three different discrete algorithms are analyzed and compared, their respective advantages and disadvantages are also elaborated. Finally, the linear combination type discrete algorithms are selected for the study. This algorithm inherits most of the properties of continuous fractional Fourier transform, and it is easy to implement in engineering.Discrete linear Combination type algorithm can be implemented in two ways, namely the serial and parallel methods. This thesis compares the two implementations. Physical resources required for parallel implementation is unbearable, but serial implementation has regular structures which is very suitable to be realized by the VLSI. Therefore, this thesis realizes a circuit by serial discrete algorithm. Through the analysis of relevant theories, this thesis presents a circuit design idea of linear combination type discrete algorithms. This design of the circuit is divided into four modules:(1) CORDIC module;(2) odd-point IFFT module;(3) matrix-vector multiplication module;(4) Logic controller module.In this thesis, the use of Baker’s prediction in CORDIC module reduces resource consumption, full use of Winograd algorithm reduces the number of multiplications in the odd-point IFFT module, and rearrangement technology improves computation efficiency of the pipeline circuit in matrix-vector multiplication module. This hardware architecture has three operation modes and can easily be extended to other fractional transforms. The proposed architecture has been verified on FPGA, which can run at a frequency up to 291 MHz while with high accuracy.