Research On Synchronization Algorithm In SC-FDE System Under Low Snr And Its Fpga Implementation

Single carrier frequency domain equalization(SC-FDE) is becoming one of the most important components of the broadband wireless commuication techniques for its strong resistance to multipath fading ability and relatively low implementation complexity. As the complement and development of orthogonal frequency division multiplexing(OFDM) technique, SC-FDE has been successfully applied to the 3GPP long term evolution(LTE) system in the uplink. At present, the reasearches on SC-FDE techniques mainly focuse on the system of high Signal-to-Noise Ratio(SNR). In fact, it shows an increasingly demand of SC-FDE techniques under low SNR condition both in the field of military communication and civil communication, a typical example is the “Weightless” standard based on White Space. As a kind of broadband wireless commuication technique, SC-FDE system is sensitive to synchronization error, and the transmmision performance is directly affected by the time and frequency accuracy.The main purpose of this thesis is to research on SC-FDE synchronization algorithm under the condition of low SNR, The main work and innovation points include:(1) Given the advantages and disadvantages of common SC-FDE synchronization algorithms, as well as the performances under the condition of low SNR, two kinds of synchronization algorithms under the condition of low SNR on the basis of Tufvesson synchronization algorithm are put forward. The two algorithms solve the problem of frequency offset estimation in Tufvesson algorithm. In addition to this, by correcting the index of symbol timing point, guarantee the correctness of symbol timing estimation in multipath channel.The Matlab simulation analysises under the condition of AWGN channel and multipath channel are also gived in this paper, and they prove the effectiveness of synchronization algorithm design.(2) The paper explains the synchronization algorithm based on the structure 1 need a great correlator, and it’s diffcult to FPGA implmentation, so another synchronization algorithm based on the structure 2 is put forward. Although the second synchronization algorithm will reduce information transmission effiency of the system to some extent, but the FPGA resources demand is also lower, and the two algorithms can achieve the same performance in theory. Finally the FPGA implementation of the synchronization algorithm based on the structure 2 is finished, and it shows the effectiveness of the FPGA design though hardware tests.