| With the rapid development of semiconductor technology, the peripheral of general MCU are more complicated. Applications with more functions and high speed are popular in common. In many SoC applications, R&D become highly complicated as it highly depended on lots of peripherals of the MCU. The requirement of the characteristics even more be reliable and safe. In the development process of our projects, we have found out that there were barely no means to monitor our peripherals at MCU level. This could lead a lot of unexpected issues during debug and test stage. And most of these issues are due to the illogically using of MCU’s resources.In this thesis, based on the ucosIII RTOS and cortex-M3 kernel, I do quantitative analysis research of ucosIII kernel and give a prototype of the hardware probe system. Primary content as below:1. based on the STM32F217 embeded on the STM3221G-EVAL evaluate board. porting the ucosIII on this type of MCU with cortex-M3 core. By doing this, we can achieve a fundamental platform for quantitative analysis and system design of hareware probe. Meanwhile we can do some similar research on different MCUs of same core without modifying upper softwares of the system. Obviously, the hardware probe system is independence from the lower specific types of hardware.2. Thanks to the newly statistics port characteristics of ucosIII, we do quantitative analysis of some primary parameters such as task creation, tasks switch times, usage of CPU and etc. By doing this, we could basically understand the performance of ucosIII and also help us for designing a better architecture of the hardware probe system.3. The hardware probe system is based on the UCOSIII. The architecture is adopted by 4 layers: hardware access layer, hardware monitor layer, data package layer and display layer. The tailorable system is independent of upper application code. Using this system can clearly know the usage of real resources and aslo guide the developer for optimizing their design works. |
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