Research On Denoising Algorithm Of Fiber Raman Distributed Temperature Sensor System

Raman distributed temperature sensor (RDTS) is a kind of new sensing system based on spontaneous Raman scattering temperature-sensitivity effect and optical time domain reflectermetry (OTDR). Due to its many advantages such as corrosion resistant, small volume and electromagnetic interference resistant, RDTS is widely used in transportation, construction and gasoline fields. However, because of spontaneous Raman scattering light is very weak, which result in low signal noise ratio (SNR) of the system, thus the real-time capability and measurement accuracy of RDTS is also restricted deeply. In order to solve this problem, the source, regularity and nature of noise are analyzed based on the principle and structure characteristics of optical fiber sensing system in this paper. The mathematical model of signal is also established in order to apply variety of denoising algorithm to improve the SNR of the RDTS. A research topic of DTS denoising algorithm is proposed.Denoising algorithms used in this paper mainly include linear superposition average algorithm, wavelet transform algorithm, empirical mode decomposition algorithm, linear coding algorithm, correlation coding algorithm and independent component analysis algorithm. Firstly to solve the problem of low efficiency of correlation coding algorithm, two improved algorithms are proposed, which are based on fast Fourier transform (FFT) and fast Hartley transform (FHT) respectively, meanwhile signal block processing is also used to improve the efficiency of decoding. Secondly aimed at the uncertainty of the independent component analysis (ICA), this paper puts forward a kind of improved algorithm, which called Fast ICA with front correction. Furthermore in order to illustrate the effectiveness of the above algorithms, Matlab software is used to simulate and analyze, and obtains a better denoising effect.Thirdly, this paper does a pilot exploration of the "hardware processing" of the algorithms. The FFT processor based on FPGA is designed. In the FFT processor, ex-situ sequential structure with reverse input and sequential output is used to implement 1024 points 24 bit numbers FFT with 10 level butterfly operation. Furthermore, simulation results by using Matlab/Modelsim validate the correctness of proposed scheme.