| In recent years, the technology of communication terminal chip develops very quickly. At the same time, the design of mobile terminals becomes increasingly difficult. Firstly, with the feature size of CMOS decreases from 90 nm to 65 nm and now to 28 nm, the related static power has become as higher as the dynamic power. So how to reduce the static and the dynamic power of the chip power network has become one of the most important issues of nanoscale IC design. Secondly, with the continuous development of IC fabrication process, chip scale becomes larger and larger. Then chip verification is more and more difficult, and it’s very easy to make mistakes when chip works. Therefore, how to reduce the verification time, how to effectively correct the error, and how to reduce the time to the market will be more and more important.In this case, the automatic flow has developed rapidly. In general, IC design can be divided into two parts, including front-end design and back-end design. Front-end design refers to from RTL design to logic synthesis, and back-end design usually refers to physical implementation. However, due to the complexity and short design cycle, back-end design often determines whether the chip tapes out successfully in a timely manner. Therefore, automatic flow has a broad application space. Automatic process decomposes the complex tool commands into several steps, and each step can be achieved by a simple command, which is defined by the designer. What’s more, the tool can also generate a log file of each step to save the steps separately, which can improve the design efficiency and simplify the error correction for designers.Based on digital baseband chip which is called XG726, ECO flow and low power flow are studied in this paper. Usually, a constantly communication is needed between the back-end engineers and the front-end engineers when doing ECO. It is needed to confirm which module needs to do ECO by the front-end engineers. After finishing ECO by the back-end engineers, the front-end engineers must verify whether the module works well. The matter of the circuit performance which is found after simulations can be modified quickly by ECO flow. For different modules, different ECO flows are used to get a reasonable patch size. Then the difficulty of the back-end implementation is reduced tremendously. The new ECO flow includes Cut Point ECO Flow and Flatten ECO Flow. Flatten ECO Flow can solve the boundary optimization issues after logic synthesis, and the Cut Point ECO Flow is fit for the flattened netlist. In addition, by setting up and testing the Golden UPF Flow in the PCIE module, the result is compared with the Base Flow result, to judge whether the new result is better. In particularly, considering Verdi-Sign Off is a new tool to check power intent and there is no Base Flow to be compared with. In this way, it is needed to set up and edit the related input files to evaluate for Verdi-Sign Off Flow. In a word, these two flows can improve the efficiency of the low power design substantially. There is a great improvement in performance by Verdi-Sign Off, compared with MVRC. Both the implementation of the related flows and the issues which need to pay attention to are from back-end work experience of digital IC design, which have a good reference value. |
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