Theory And Hardware Research Of Codes And Modulation Technology Based On LDPC Code

In communication system, channel coding and modulation technology is one of the most effective ways for increasing the efficiency of transmission. For this reason, this thesis focuses on the theory research and hardware implementation of code and modulation technology.Firstly, this thesis introduces the common digital modulation technology and Orthogonal Frequency Diversity Modulation (OFDM) technology. Then, we investigate the traditional encoding and decoding algorithms for LDPC code and present a new kind of efficient decoding algorithm. By simplifying the calculating and storing process, new decoding algorithm named Semi-parallel Fast Scan Decoding (SFD) has reduced the calculating complexity and improved decoding speed, which save up nearly50%resources consumption. Besides, we also implement the algorithm in FPGA. Through the use of some optimization technologies such as ping-pong buffer memory, multiple decoding cores, and two-stage pipeline, the encoder and decoder implemented in FPGA can get a high throughput. The practical result shows that when the number of decoding iteration is10, the throughput of whole link is all above100Mbps for different code-rate LDPC code and the performance loss is less than0.1dB.At the same time, this thesis continues to make a research on the technology of combinational optimization of coding and modulation. In this aspect, we present a new kind of combinational optimization technology named Joint Coding and Modulation Diversity (JCMD). By introducing rotated modulation and component interleaving, this new technology increases the diversity of communication system and can get obvious performance gain. The simulation result shows that the performance of JCMD transmission scheme in AWGN channels is nearly the same with that of Bit-Interleaved Coded Modulation (BICM) transmission scheme, but the performance of JCMD in multipath channel can get2dB gain compared with that of BICM scheme. Finally, we implement JCMD and BICM in FPGA and the hardware result shows the advantage and feasibility of JCMD.