Design And Implementation Of The Phy Layer Of An Indoor Visible Light Communication System Based On FPGA

Visible light communication using LED is a kind of wireless optical communication technology that rising in recent years. Benifiting from some features of LED, such as low power consumption and short response time, indoor application of this technology combines the two functions of lighting and communication. With the progress of study, new type of high speed LED is invented for this technology. Technologies such as OFDM, MIMO and equalization are applied in visible light communication system. As a result, rates of system continue to create new records; the latest offline rate of10Gbps has been reported. However, aspects of research on system networking, system hierarchy, upper layer protocol and physical layer protocol are lagging behind. In this disertation, we present some of our study results on indoor visible light communication system. The main content of the disertation is as follows:1. Hierarchical design concept is adopted for indoor visible light communication system. An overall framework of the system is proposed. To solve multi-user accessing problem in visible light communication ystem, MAC layer based on CSMA/CD, MAC layer based on CSMA/CA and MAC layer of IEEE802.15.7standard are studied and compared.2. An indoor visible light communication sytem based on IEEE802.3standard MAC layer is presented. In this system, a visible light communication PHY layer is connected to the IEEE802.3standard MAC layer via the media independent interface (MII). The proposed solution dose not require re-design of a new MAC layer, but also ensures the compatibility between the indoor visble light communication system and existing Ethernet.3. Collision detection method for multi-user accessing in the system is discussed and a feasible solution is given. In this solution, tranciever circuit of the AP is improved to support collision detection. Diagram of the corresponding collision detection scheme at the terminal end and AP end are presented.4. Based on the work above, block diagram of the digital module of the PHY layer is given. The PHY layer protocol, coding scheme and data signal processing are described in detail. State transition diagrams of every block are given. All functions of the digital module are realized by Verilog HDL.5. An experimental sytem is build to verify the performance of the system. The sytem implemented can be used for visiting website, transfering files, and the data rate is surfficient for HD IPTV video.