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Research And Implementation In Face Gender Recognition Algorithm Based On FPGA

Posted on:2012-06-01Degree:MasterType:Thesis
Country:ChinaCandidate:H L LiFull Text:PDF
GTID:2298330467978613Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Face gender recognition technology is developed based on face recognition technology, and it has a wide wide application perspective in many fields, such as information acquisition, identity authentication, electronic monitoring, and intelligent service robot.In this paper, Altera Quartus II and Nios II software are used to design a face gender recognition system based on FPGA (Field Programmable Gate Array), while Cyclone II family DE2development board is adopted as hardware platform. This article uses the Quartus II software to design and implement face gender recognition hardware system, and uses Nios II IDE to develop software system using C programming language. The main work of this paper on face gender recognition system is listed as following:(1) This article uses the Principal Component Analysis(PCA) algorithm for image feature extraction, and the feature vectors is used as the classifier input vectors.(2) This paper designs two different classifiers using BP neural network and support vector machine(SVM), and compares the recognition rate of the two classifiers. Recogniton rate of SVM using Rbf radial basis, linear and polynomial kernel functions is compared. The results show that SVM classifiers are better than BP network classifier and the performance of classifers vary when using face images with different gender.(3) Due to the recognitin limit of using single classifer, this paper presents a classifier using parallel classifier group and hybrid classifier group based on the previous cascade SVM classifier. Experiments are carried out to test the performance of parallel classifier group, hybrid classifier group and cascade SVM classifier. The results show that,hybrid classifier group obtain the hignest recognition rate and parallel classifier group get the lowest recognition rate.(4) The face gender recognition hardware system is realized in this paper. Using SOPC Builder tool of Quartus II, the face gender recognition system base on NiosII processor is built. And the system is tested on MIT face database. The result shows that the recognition rate of the system designed in this paper is97%, and the recognition time for one image is less than0.01s.
Keywords/Search Tags:FPGA, Support Vector Machine, Principal Component Analysis, BP network
PDF Full Text Request
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