Scalar Multiplication Design And FPGA Implementation For ECC On GF(2~m)

After the public key cryptography-elliptic curve cryptosystem which based onelliptic curve discrete logarithm problem is proposed, it quickly set off a huge wavein the academic study of ECC. Because compared to other cryptosystems such as thepopular RSA key system, ECC key is shorter and has higher safety performance.Currently, it is widely used in secure communication, fast encryption, authentication,digital signatures and other areas. Many areas, such as the European Union, SouthKorea and China are all serve as the password for standard applications in themainstream of information security in many areas, we will wait and see.Originally, elliptic curve cryptosystem problem is a extension of the basicmathematical problem. In this paper, we made a thorough inquiry of the problem inelliptic curves, number theory and other mathematical problems, aims to identify thetheoretical basis of ECC breakthrough research. Based on this, we focuses on thehardware design of elliptic curve algorithm scalar multiplication core module, andcomplete its done with the FPGA platform.Scalar multiplication is structured to achieve, it contains the upper layercomputing operation and the underlying computing operation. In the realization of thefinite field arithmetic operation and the elliptic curve underlying, we use series andparallel hybrid multiplier structure to balance computing speed and resource conflictarea. In this paper, we explore three modular inversion algorithm implementation, wechose Itoh and Tsujii based on polynomial algorithm from the perspective of resourceconservation. While seeking a more efficient scalar multiplication algorithm suitablefor hardware implementation, we made full account of the scalar multiplicationalgorithm complexity and efficiency, we use the Koblitz curves which recommendedby the NIST(National Institute of Standards and Technology, the National Institute ofStandards and Technology). Expand number of binary fields GF(2m) is m=233.The core operation of the upper part is operation kP, that is what we call thescalar multiplication, we made a thorough inquiry for fast algorithm of kP. The finalchoice is the projection coordinates Montgomery algorithm and gives its FPGAimplementation of hardware solution. We use a top-down approach to design digital circuit based on the QuartusⅡ10.0of Altera company. We use Verlog HDL hardware description language toachieve a group of elliptic curves over finite fields arithmetic and upper kP operation,and use a variety of methods to verify the correctness of the design in this article.