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Research Of SSRF Storage Ring Beam Orbit Interlock System And Application

Posted on:2016-10-08Degree:MasterType:Thesis
Country:ChinaCandidate:H L GengFull Text:PDF
GTID:2298330452466558Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
This thesis is based on SSRF(Shanghai Synchrotron Radiation Facility). According to theanalysis of the machine fault during the accelerator operation, research of the storage ring beamorbit interlock system and data analysis is carried out.The main purpose of the thesis is to upgrade the beam orbit interlock system, achieve thediscrimination of the Libera interlock signals of the storage ring, and latch turn-by-turn data ofall the BPMs in a same turn, acquire turn-by-turn data and analyze the beam abortion.The main contents of this thesis are given as followed: Fiber transmission network andtransfer interlock signals by fiber; Distinguish the interlock signal; Latch and analysis of theturn-by-turn data when an interlock occurs.In the new system, we used FPGA to analyze140signals, and output lath signals to allBPMs at the same time. It makes full use of FPGA high-speed, multi-channels digital inputs andoutputs characteristics. Interlock signals come from the stations around the storage ring.Interlock signals transfer along the optical fiber, the fiber optical transceiver is designed andtested to archive required performance. At last, laboratory testing was carried out. The test resultverified the integrity of the functions of the new system.During the accelerator machine study time, we replaced part of the old modules. The resultof the test shows that the new system can distinguish the order of interlock signals from Liberaelectronics, and trigger all Libera electronics to latch turn-by-turn data at the same time.According to the analysis of the turn by turn data, the accuracy of the measurement results hasbeen verified. The changes of beam orbit were observed during the beam abortion.
Keywords/Search Tags:SSRF, beam orbit interlock, turn by turn, LabVIEW FPGA, ASYN
PDF Full Text Request
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