Design Of Multi-path Echo Cancellation System Based On FPGA

Repeater is essential in the modern cellular communications network. Itimplements the function of relaying signals between the base stations, mobiledevices and enhancing signals during the transmission. Its basic function isequivalent to the RF signal power amplifier. However, if the isolation between thereceiving antenna and the transmit antenna is not enough, The delayed output signalfeedback to the inputs and leads to self-excited repeater, serious distortion of theoutput signal, quality deterioration of the signal waveform, serious impact on callquality, and even dropped calls. Repeater self-excitation has been the mainimpaction on repeater’s further promotion. Interference cancellation is a technologyfor dealing with repeater oscillation, and it’s also an important issue in the area ofsignal processing. So, this paper focuses on how to use the digital technology tocancel the echo signal.The paper begins to analyze the principle of CDMA same frequency echogeneration, digital repeater echo signals and echo channel, coming up with theprinciple of digital echo cancellation based on the classical echo cancellation. Echocancellation, whose key is the design of adaptive filtering algorithmic, is realizedthrough the following three steps: firstly, estimating characteristic parameters in theecho path, secondly, generating an estimated echo signal by simulating echo path,and finally, using the received signal minus the analog echo signals.The paper introduces the basic working principle and technical indicators of theCDMA frequency repeater. It also presents the overall framework of digital echocancellation system according to design specifications, which includes digital up anddown convert modules and the adaptive filter processing modules. To achieve thebest performance of the system, the research focuses on analyzing the specificimplementation process of filters in the digital up and down convert module and theadaptive filter processing module, selecting the appropriate algorithm, minimizinguse of FPGA resources while satisfying the timing requirements according torequirements. The digital down convert module is composed of the digitaldown-mixer processing module and the three decimation filter, while the digital upconvert module composed of digital mixer processing module and three interpolation filter. The analysis of this study mainly illustrates FPGA implementation of11-order half-band down sampling filter,87-order shaping filter,15-orderinterpolation2filter and8on the sample order DLMS adaptive filter algorithm.11order half-band down sampling filter is achieved by using folded structure andre-timing technology, while the87-order shaping filter using DA algorithm,15-orderinterpolation2filter on the sampling method used to achieve folding factor,8-orderDLMS adaptive algorithm filter module division and re-used time technologies.In order to verify the basic functions of each module in this digital echocancellation repeater system, this paper built a simulation environment with thecombination of ChipScope, MATLAB and Modelsim software. First of all,generating a corresponding excitation source, which will be fixed-point computated,according to algorithm of each module in the MATLAB simulation software, andthen comparing simulation results of fixed-point MATLAB and Modelsim simulationfiltering. Finally, analyzing the internal FPGA data, which is captured in thesimulation environment of ChipScope, on the simulation platform in MATLAB.This design of the echo cancellation system can cancel the echo signal.