Design Of Parallel Computation And Interface For Integrated Navigation Based On Nios Ⅱ

SINS/GPS(Strap-down Inertial Navigation System/Global Positioning System)integrated navigation is combined the autonomy and continuity of SINS with the highprecision of GPS which was a kind of integrated navigation that come out in recentyears. Plane, vessel and other application fields put forward stricter requirements onreal-time of the navigation day by day because more and more high dynamicapplication have occurred. Thus leads to make high real-time becoming an importantdevelopment direction of modern navigation system. The article aiming to promotethe real-time of the SINS/GPS integrated navigation system, design the computationstructure of the system, a parallel method to deal with matrix calculation and a moduleto acquire navigation parameter.1. Divide the integrated navigation system into some parts; design the parametercollect module for navigation device and GPS. The parameter collect module havesuch function: multi-channel ADC7606-6control cell which was designed in Veriloglanguage, FIFO(first in first out)which serve as data buffer, the acquisition oftelegraph text of GPS.2. Design a double Nios II system for navigation system which have insidemodule-building, outside storage selecting, double CPU mutual exclusion accessincluded. In this way, the advantage of Nios II system could be made full use of.Compared with the FPGA with double DSP system, this method would gainhigh-performance in navigation system. The detail advantage is parallelism and theability of reducing the signal delay.3. In strap-down inertial navigation system (SINS), the floating-point matrixmultiplication is complicated and time-consuming. Therefor the calculation is aconstraint of developing SINS’s real-time. To solve the problem, a sort of parallelmethod applied in Nios II system is put forward. The core of this method ishigh-performance matrix multiplication cell whose structure is formed on systolicarray basis with optimizing by loop tiling, data space diving and iteration spacecombining. Together with the remarkable speed advantage of DMA (Direct MemoryAccess) for mass data exchange, the operating rate of matrix multiplication is boostedfurther. The result of test illustrates that the accelerator has ability to carry out the specific computation accurately and fast, its speed performance is especiallyprominent.