Implementation Of Hash Algorithm Multiplexing IP Core And Design Of Anti-attack

In this paper, a high-performance multiplexed IP core is designed, which is usedas the encryption algorithm module in the design of security SOC chip and can realizeits functions and performance by experimental verification. Information security is amajor issue of concern at home and abroad, so security chip SOC as the hardwarecarrier of information security technology has been widely applied. Informationsecurity issue prompts the development of cryptography so that encryption algorithmas a kind of effective security technology has been researched and used deeply. Forthe SOC chip, the hash algorithm becomes the core algorithm as its superior securityperformance. In recent years, there are many IP designs on hash algorithm, but mostof them are special cipher processing chip to achieve a settled cryptogram algorithms.And they are for a particular kind of encryption algorithm, unable to meet themultilevel security requirements for using the different cryptogram algorithms users.Based on security SOC chips, the paper designs a multiplexed IP core that iscompatible SHA-1, SHA-224and SHA-256three kinds of algorithm. The IP coreuses the32-bit data bus technology and supports for8-bit,16-bit and32-bit datareading and writing, so it has a strong flexibility in transplantation and use. The IPcore with space saving, resource optimization and good transplantation satisfy themultilevel security requirements for using the different cryptogram algorithms users.Also, it supports double reset, interruption, and low power consumption mode, toread and write operations when algorithm is running. The paper further study of someof the most popular is the most effective means of attack, in SHA-IP has carried onthe research and design, against the attack to guaranteeing the safety of the chip. Thepaper further studies some of the most popular and effective means of attack currently,and gives the design of the anti-attack in SHA-IP so as to guarantee the safety of thechip.On the basis of in-depth study of the three algorithms and using the connectionand similarity between each other, the paper improves and redesigns the threealgorithms which quicken the speed of operation and improve the operation of core properties. After completing the study and design of the algorithm, the paper realizesthe hardware implementation of IP. At the same time, it not only describes in detailthe logical structure design and optimization but also mainly introduces the overallstructure of the multiplexed IP core as well as the implementation of each functionmodule. Following the design of the code, it begins the function of the modelsimulation validation through checking the complied style. The paper mainlyintroduces the key work, for the rest of a front-end and back-end design only makes asimple description. Upon completion of the RTL code, the paper begins the logicalsynthesis, formal verification, time series analysis, layout, and focuses the key workabout the main mode of functional simulation of the IP core on the platform. Thesimulation using the real CPU and data bus is the important part of verifying the chipfunction and the error correction. In the process of design of the IP core, every linkhas been verified in detail, including the schema validation, the main mode platformvalidation, the post simulation verification, FPGA validation and the finished producttest validation. After the completion of the IP, the paper analyzes the powerconsumption and performance of the IP core and, reflects the strong advantage of theIP core compared with the similar products. Finally, according to the chip facingattacks, a more comprehensive exploration and research are in an all-around, and thedesign of anti-attack aimed at the main attack way can effectively resist the attack ofhacker, increase the safety of the chip. In the design, several innovative works aremade:First, using the inner link of hash algorithm, the paper redesigns the algorithmand achieves the design of the IP core multiplexing with SHA-1, SHA-224andSHA-256. Besides, it can meet the multilevel cryptographic security requirements andgreatly increase the safety at the same time.Second, based on the in-depth study of the algorithm and repeated researchhardware, all are designed and optimized in the algorithm and logic structure. Thatmakes the multiplexed IP core in computing speed, performance, space, portability,resource optimization and integration optimization has a huge advantage.Third, the security encryption chip facing attacks carries out in-depth andcomprehensive study and anti-attacks are designed for the mainstream attack, aiming at greatly improving the security of reusable IP cores.Because of its superior operational performance, comprehensive safetyperformance, strong portability and other advantages, the IP core has been as a digitalsignature IP core in a variety of SOC chip. Chip containing the IP has passed thetechnical appraisal, and get a higher rating in the evaluation of similar products.