Research On The Adaptive Digital Pre-distortion Technique

In order to increase the signal coverage area, public mobile communication basestation usually adopts power amplifier to amplify signals to be transmitted. However,the nonlinearity of the power amplifier will cause signal nonlinear distortion,reducing the power amplifier efficiency. In order to improve efficiency of the poweramplifier, it is necessary to compensate the nonlinearity of the power amplifier.Digital pre-distortion technology is the most widely used way to compensate theamplifier nonlinearity.In order to choose an appropriate amplifier behavioral model for the digitalpre-distortion algorithm, this paper analyzes several mathematical models of poweramplifiers, including memory models and memoryless models. In order to fasten theconvergence of the fixed step size LMS algorithm, a modified variable step size LMSalgorithm, whose step variation is proportional to the product of current error andprevious error, is proposed in this paper. The proposed algorithm can well restrain theinstant noise interferences without increasing the computational complexity. Thesimulation results have shown that compared with the existing variable step size LMSalgorithms, the convergence speed of the proposed algorithm is similar, but itssteady-state error is much smaller. Meanwhile, its computational complexity is lower,which favors of hardware realization. Then the algorithm is applied to the digitalpre-distortion simulation project built based on the System Generator. We conductedsome experiments for the memoryless power amplifier model and memory model.The experimental results have shown that compared with the fixed step size LMS, forthe memoryless power amplifier, the ACPR gain is about15dB, and the convergencespeed is1.5times faster; for the power amplifier with memory, the ACPR gain isabout10dB, and the convergence speed is1time faster. When using the Least Squarealgorithm to update the coefficients, the ACPR gain can achieve30dB improvement,the convergence speed is15times faster than the fixed step size LMS. However, theLeast Square algorithm costs lots of logic resources, so it can be only implemented in the Vertex series FPGA. Considering that when realized in a FPGA, the plural formLMS algorithm is required, a plural form LMS project for FPGA is set up, and thealgorithm is verified by simulation. The digital down conversion and digital upconversion projects are also established to confirm that the conversion betweenmid-frequency signal and baseband signal in digital mid-frequency board workingwell. The vector signal generator and spectrum analyzer are applied to verify itscorrectness.