Investigation On The Monocrystalline Silicon Surface Passivation And HIT Solar Cell Performance Improvement

Further reduction of photovoltaic(PV) system cost is a determinative factor to promote the application of the solar PV energy. The relatively low conversion efficiency and the too high fabrication cost of solar panels are the two main factors that limit the system cost reduction. The heterojunction with intrinsic thin-layer(HIT) solar cell is one of the most promising technologies that enable both high efficiency and low cost.In this thesis, the surface passivation of monocrystalline silicon(c-Si), a key technology of HIT solar cells, is first studied. By inserting a high-quality intrinsic amorphous silicon(a-Si:H) layer between the c-Si wafer and the doped a-Si:H layer deposited by a low-damage plasma enhanced chemical vapor deposition(PECVD) process, the surface dangling bonds of c-Si can be well passivated. The effect of silane concentration, working pressure, RF power and flow rate in the PECVD process on the silicon wafer surface passivation are systematically investigated. With the optimized deposition parameters in PECVD and wet cleaning process, as well as a fine-tuned post-annealing treatment, a highminority carrier lifetime over 4 ms was obtained in the structure of a-Si:H(i)/c-Si/ a-Si:H(i). It is found that a certain combination of deposition temperature and post annealing temperature results in significant improvement of the minority carrier lifetime. By the optimization of the deposition parameters in the PECVD process of n-type and p-type a-Si:H(a-Si:H(n) and a-Si:H(p), respectively) thin films, together with a post annealing treatment, high conductivity, up to 100S/cm for a-Si:H(n) and 10-5S/cm for a-Si:H(p), are obtained. With optimized a-Si:H layer deposition parameters and the post annealing treatment, high minority carrier lifetime of 3.7 ms was achieved in a a-Si:H(p)/a-Si:H(i)/c-Si/a-Si:H(i)/a-Si:H(n) structure.The relationship between minority carrier lifetime and the performance of the HIT solar cells is investigated. It is found that with the increase in minority carrier lifetime, open circuit voltage(Voc) of solar cells increases sharply, until it begins to saturate as minority carrier lifetime exceeds 2 ms. Thus, minority carrier lifetime can be used as an efficient criteria for in-situ production monitoring. Such observation was explained by quasi-Feimi level splitting in the solar cells.a-Si:H(p) layer quality is very crucial for n-type c-Si wafer based HIT solar cells.It is found that a-Si:H(p) deposited at a moderate temperature(150oC) followed by an annealing process at a relatively high temperature(200oC, for instance) allows higher conductivity and better surface passivation of silicon wafer than that deposited directly at high temperature of 200 oC. High performance is observed in an HIT solar cell with such improved p-layer, in which Voc increases from 663 m V to 700 m V, efficiency, fill factor and short circuit current reach 16.26%, 72.35% and 32.10 m A/cm2, respectively.With optimized grid electrode and the contact resistance between metal and semiconductor, an HIT solar cell based on surface-textured CZ c-Si wafer exhibits high efficiency of 17.2%.