Design Of A Broadband Synchronous Fast Response Buck DC/DC

With the integrated circuit technology continues to break barriers, the performance of electronic products get better. The demand for good power supplies is expanding. Switching power supply is widely used in the consumer electronics, industrial control, mobile communications and other applications. High accuracy output, low EMI, fast transient response is a hot topic in DC/DC design. Different control mode often has different properties. Generally, for different application conditions will choose the appropriate control strategies to meet the requirements of the application environment. Currently, one of the research hotspot is the use of phase-locked loop(PLL) technology to the traditional DC/DC so that the operating frequency can be locked, in this way the EMI spectrum can be determined. To do so is conducive to design EMI filter which is used to filter EMI. Therefore, the focus of this paper is to lock the DC/DC switching frequency.Firstly, this paper analyzes some control mode of DC/DC, whose operating frequency can be fixed. The advantages and disadvantages of each of these control modes are analyzed. Taken together, the paper will give a new structure which use PLL to lock the operating frequency of DC/DC. Therefore, this paper analyzes the basic principle of the PLL and each composition of PLL is analyzed. The function and principle of each module is analyzed. Mathematical model of each sub-module is derived and The PLL open-loop transfer function is analyzed. On the basis of theory, a PLL system is designed in this paper. The system combines the PLL and DC/DC together, looking the DC/DC as the VCO of PLL. Successfully using PLL technology lock the switching frequency DC/DC.The circuits of this paper use CSMC 0.25μm BCD process. After the circuit design is complete, each sub-module uses Hspice to simulate. After the correctness of the design of each sub-module has been verified, the entire system is simulated. The results show that in the frequency range of 200 kHz to 2MHz, PLL can achieve lock switching frequency. For PLL loop stability, first derived its open-loop transfer function, and then go on behalf of the design parameters, using MATLAB simulation of the AC characteristics. The simulation results show that the unity-gain bandwidth of the system is around 17 kHz, and the phase margin is 57 degrees which meet the requirements of stability.