A Design Of Fly-back LED Driver Power Supply Chip With PFC

LED, as one kind of green lighting, represents the fourth generation electronic lighting. With the advantages of high luminous efficiency, small volume,good color rendering, long life and environmental protection, the traditional lighting with be replaced by LED sooner or later. However, due to the disadvantages of high price, incompatibility with LED, the development of LED lighting is restricted. In LED driver, switching power supply driver is widely used because of its small volume, high efficiency and high reliability, etc.In this thesis, a fly-back LED driver chip with Power-Factor-Correction function and primary-side feedback is introduced. This chip is always used in low power application. Its output current is high up to 370 m A and the variation of the output current is error less than 3 percent. Besides, this chip with high power factor(0.95) i s able to improve power efficiency. While using primary-side feedback simplifies the control loops. To reduce the output current ripple and EMI, the chip operates in current boundary conduction mode(BCM).Based on the actual application requirements, we set the chip functions, such as, a constant output current and Power Factor Correction(PFC).Then the functions of the sub-modules are determined through comparing the different structure the overall circuit structure and the working mode. Three modules are described in this these in detail, including zero current detection and over voltage protection module、current peak limit and latch module、logic control module. The zero current detection is to make the circuit operate in critical current mode. The current peak limit module is used to limit the current peak of input current and make the phase same with the input voltage to realize the function of power factor correction. The current peak latch module latch the current peak for achieve constant current. The logic control module control the state of chip.Based on sub-modules functions, The detail circuits were designed and verified. Finally, the chip was simulated combined all of sub-modules with perimeter topology.