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The Design Of Controlled Fault Interruption And The Accomplishment Of Monitoring

Posted on:2015-02-12Degree:MasterType:Thesis
Country:ChinaCandidate:S J DaiFull Text:PDF
GTID:2272330467985437Subject:Electrical engineering
Abstract/Summary:PDF Full Text Request
With increasing load and voltage of the electrical power system, damage of short-circuit fault becomes larger. Controlled Fault Interruption (CFI) uses the method of predicting zero point of the fault current to reduce the arc energy producing when the circuit breaker is opening and thus the influence of short-circuit fault is decreased.In order to predict the zero point of the fault current quickly, the parameters of the fault current must be restored precisely during ultra short time. This thesis employs modified Least Squares method and models the nonlinear fault current by taylor expansion. There is an error because only the first two terms if the taylor expansion are took into consideration. Thus time constant compensation method is applied to correct this error. The influence of variable parameters towards predicting error is tested using MATLAB. At last, the threshold to judge whether the fault happens is obtained by the method of F detection. MATLAB is used to simulate the fault judging error and corresponding method to judge the fault and interrupting strategy are put toward.This thesis designed the CFI controlling circuit base on FPGA chip for the application. EP4CE15F17C8N is chosen as the central FPGA chip. TC35is chosen as the communicating chip and AD9226is used to sample. The design and fabrication of the PCB are accomplished.At last, the software design based on Verilog HDL language for control is finished, including data processing module and data uploading module. The upper computer design is finished by using MFC paint in C++language. Simulation fault current is produced by relaying tester. And use the fabricated controlling circuit to detect. The detected fault current data are transmitted to the upper computer for display. Apply MATLAB to analysis the experimental results, it reveals that the fabricated controlling circuit can predict the zero point of the fault current precisely. And the upper computer can restore the curve of the fault current.
Keywords/Search Tags:Controlled Fault Interruption, FPGA, Modified Least Squares Method, FaultCurrent, Target Zero Point
PDF Full Text Request
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