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A Design Of Missile Borne Data Recorder Based On SoC

Posted on:2015-02-06Degree:MasterType:Thesis
Country:ChinaCandidate:C J XiaoFull Text:PDF
GTID:2272330464468572Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
The data recorder device is an important part of the missile test system, mainly used to record various parameters of the missile during flight. At present more and more missile design research background, puts forward the higher index of traditional design of missile borne recorder, it is required to adapt to the characteristics of the testing signal diversity, real-time. Therefore, the development of a universal and excellent missile borne data recorder that can meet all kinds of test requirements becomes very necessary.In this context, a design of a kind of data storage equipment with the basic architecture of So C plus NAND FLASH is proposed to meet the system requirements successfully.In this thesis, firstly, according to the special requirements of recorder equipment load in elastic working environment, appropriate So C and NAND FLASH chips are selected and the entire design architecture is given. Secondly, we describe in detail the hardware design of the system, mainly include the schematic design of the main control board and storage board specifically including the design method and the principle of power, clock, boot load, interface etc. Then, mainly introduces the software realization of the main control board, the main developing procedure of the Zynq 7000 So C, the development of Gigabit Ethernet based on it, and the high-speed transmission with the storage board. Finally, expounds the software realization of the storage board, the user-defined data transmission protocol and the system work flow are also introduced, at the same time, illustrates the design idea and implementation method of bad block management, storage array erase, record, read back and ECC parity function. This paper completed the hardware and software design of the data recorder system which is based on So C plus NAND FLASH architecture. In the process of debugging many problems were encountered and solved. The paper has a certain engineering reference value for the design of high-speed large capacity data storage device.
Keywords/Search Tags:Zynq So C, FPGA, NAND FLASH, Data Recorder
PDF Full Text Request
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