The Design Of Portable BER Analyzer With Rich Interfaces Eased On Android And FPGA

With the rapid development of modern communication technology, digital communication has taken the dominance and lion’s share. Compared with analog signal, digital signal is easy to be regenerated, encrypted and processed. In addition, digital circuit is more reliable. With the digital communication’s large-scale application, investigating and evaluating digital communication system validity and reliability becomes an important issue in front of us. Reliability is the most basic, the most important index of digital communication system, an equipment to measure the reliability index is BER(bit error rate) analyzer. Table ber analyzer which is bulky and powerful, and has a standard interface, is very important. But portable ber analyzer with small volume, rich interfaces, continuously variable rate, is more valuable for fieldwork.In this paper, the BER analyzer is designed by the mode of "analyzer/generator". By using the DDS module, the generator produces a clock signal with continuously variable frequency to the "m-sequence generator" which produces pseudo random sequence sent to the testing system. The analyzer synchronizes and regenerates the data/clock signal come from the testing system, and the local m-sequence generator produces local m-sequence by referring the regenerated clock. Comparing the local m-sequence with the regenerated data sequence, we can find the errors. In detecting error process, we need synchronize the two compared sequences. In order to avoid loss the synchronization state when an error occurs, the’buffer pool’solution is proposed which can ensure the state synchronization. The principle is that, the error code is input to the pipe inlet, the correct code is output from the pipe outlet. Every code opens one time the pipe inlet and outlet, and some water will be poured into the pool or flow out the pool. If the water overflows the pool, the asynchronization state appears. By adjusting the pipe inlet/outlet diameter, the synchronization state can be protected effectively and the asynchronization state can be response rapidly. To meet the user special requirements about the test sequence, the design also provides a maximum of32-bit user-defined test sequences in addition to the standard m-sequence.This designed ber analyzer achieves the function of error analysis by VerilogHDL. And based on Altera’s EP2C8Q208, building SOPC to control the whole hardware circuit and the communication with epigynous machine. AD9850which uses DDS technology provides a continuously variable clock for ber analysis module. Application software is written to achieve man-machine interface function base on Android embedded OS.The designed portable ber analyzer provides a continuous variable test rate:0.001-2048kHz; HDB3, AMI, RZ and NRZ four kinds of balanced/unbalanced interface;7m sequences of different rates and user-defined test sequence;0.1-10s continuously variable gate time;7insertion error rates;4different synchronization protection sensitivity. The ber analyzer has the advantages of small volume, powerful function, rich interfaces, and works perfectly for capturing design goals.