MRI Dual-channel Digital Receiver

With non-invasion, non-trauma and high spatial resolution, Magnetic Resonance Imaging (MRI) now is widely available for clinical applications. However, the speed of MRI and the temporal resolution are not high enough compared with other imaging methods. Therefore it is important to study fast magnetic resonance imaging technology. The development of fast magnetic resonance imaging technology and the cooperation of different disciplines put high requirements on the MRI system in both software and hardware. Parallel magnetic resonance imaging (pMRI) technology has played a key role in accelerating image acquisition. And pMRI technology requires participation of multiple channels for signal acquisition in MRI system.This thesis proposes an improvement project for "duo-channel digital receiver" based on the requirement of fast magnetic resonance imaging. First, combining the data cache technology and PCI bus, the logical control of the local storage (SDRAM) is modified for higher working efficiency by using the advantage of parallel execution of modules in FPGA. Sampling and uploading data can be executed parallelly, which accelerate the data acquisition effectively. Next, an inside-trigger mechanism is designed to generate a sampling-trigger signal for the receiver itself which can complete a whole series of sampling operations on its own under the control of the synchronization signal. It can be switched to the external-trigger mechanism by FPGA register, which means that the receiver can be used in both distributed MRI system and integrated MRI spectrometer.The main contents of this thesis include:First, the basic principle of MRI digital receiver is introduced in this part. It includes software radio theory and the working principle of the main parts of digital circuits.Second, the hardware design of the receiver is elaborated. The logical program running in FPGA is described in details as well.Third, the test results of the receiver mentioned is presented.