High-speed ECC Accelerator Resistant To Power Analysis Attack

With the growing demand of information security,1024-bit RSA algorithm commonly used isfacing serious security threats currently, and elliptic curve cryptography (ECC) has significantadvantages in terms of security and processing decryption rate compared to the RSA algorithm. Inorder to ensure cryptographic applications’ security of economic areas, The State EncryptionAdministration has developed a national standard ECC algorithm(ie. SM2algorithm), andpublished the relevant standards and specifications, and the RSA algorithm is required replacingwith SM2algorithm. Meanwhile, side channel attack technology against ECC algorithm, especiallypower analysis attack is very threatening. By analyzing the power assume leakage to attack ECCalgorithm. Therefore, how to achieve high-speed ECC algorithm with resistance of power analysishas been and will be the focus point of the cryptography industry.This paper introduces the design of ECC accelerator IP on prime field for the SOC design,presents a secure and efficient and easy to implement ECC algorithm scheme, which is suitable forhardware implementation. After the verification of scheme’s correctness and feasibility withsoftware, the paper implement the ECC accelerator RTL design with verilog Hardware DescriptionLanguage, and verify the accelerator’s correctness and performance with detailed simulation andlogic synthesis. And, the paper also set up the power analysis attack platform for encryptionalgorithm, in order to verify ECC accelerator’s resistance to power analysis attack.This accelerator supports192/256bit elliptic curve application, and supports fixed-based singlemultiplication and simultaneous point multiplication, where rapid simultaneous pointmultiplication with left to right real-time joint form coding is proposed in the base of Shamiralgorithm. Under200MHz frequency, the Accelerator IP can fulfill5000times signature and1600times verification per second in256bit prime field based on SMIC0.13um process. Which havereference value for the development of high-performance security chip product.