The Key Technology Study Of Non-volatile Memory Based On Standard COMS Process

Electronic products，SOC(System On Chip) or ASIC designs often require a small amount ofNVM (from dozens of bits to few Kbits), but the traditional NVM needs multi-layer polysilicon toform the floating gate device, compared to a standard CMOS, its manufacturing process requiresadditional mask and extra process steps, not only the production cost is high but its process ismore complexity, and it is hard to integrated in SOC systems. Due to the need of high voltageabout15V to erase or write information, it leads to high power consumption at programming, sotraditional NVM are not suitable for low-power, low-cost applications (such as RFID tag chip).This paper mainly studies the pure logic NVM based on the standard CMOS process.According to the UHF RFID application, this paper innovatively uses standard CMOSprocess to design a pure logic non-volatile memory, called MTP (In this paper, the research objectis called MTP); and then put forward the corresponding memory array. The gates of two MOScapacitors are connected to form floating gate, which is used for information storage. The towconnected MOS capacitors, one is larger than the other, and the large one is equivalent to thecontrol gate capacitor (it is similar to the control gate in Flash and EEPROM). The control gatecapacitor controls the voltage in floating gate to form the required electric field to generate FNtunneling effect. The tunneling effect is used to complete capturing and removing the charge inthe floating gate.In addition, this paper also innovatively designs the new charge pump system, introduces fastand slow clock to complete the high voltage boost, which consists of two step climbing, thismethod makes the overall rise time elongated, and reduces programming power consumption;besides, in order to reduce power consumption, the capacitive divider is used to detect voltage;using the full PMOS to design the new doubler, which reduces the charge loss in transmissionprocess; the four phase clock is introduced to prevent reverse leakage current, the voltage doublerdouble efficiency is above60%at the voltage low to1V, to ensure that program of MTP issuccessful at low voltage.We use Spectre EDA tool to design the circuit, Hspice and Spectre is used for circuitsimulation; The simulation results show that, for MTP designed in this paper, the minimum readvoltage is1V, power consumption is about1uW; minimum programming voltage is about1.3V, the power consumption is about15uW; compared to the traditional EEPROM, MTP designed inthis paper has very obvious advantages.